This invention relates to error correction circuitry and more particularly to error correction circuitry that can provide data recovery during extended drop out periods of a high speed serial link with an embedded clock signal.
Typical error correction techniques, such as, for example, forward error correction (FEC), allow a receiving device to detect and correct corrupted data that contains fewer than a predetermined number of errors. FEC techniques add extra bits or bytes to each transmitted data character or code block using a predetermined algorithm.
An increasingly important type of signaling between devices is serial signaling in which the clock signal information is embedded in or can be derived from the serial data stream so that no separate clock signal needs to be transmitted. For example, data may be transmitted serially in packets of several successive serial data words preceded by a serial header that includes several training bits having a predetermined pattern of binary ones and zeros. The clock signal information is embedded in the data signal by the high-to-low and/or low-to-high transitions in that signal, which must have at least one high-to-low or low-to-high transition within a certain number of clock signal cycles. At the receiver, the clock signal is recovered from the data signal for use in properly processing the data signal. For convenience herein, this general type of signaling will be referred to generically as “clock data recovery” or “CDR” signaling.
CDR signaling is now being used in many different signaling protocols. These protocols vary with respect to such parameters as clock signal frequency, header configuration, packet size, data word length, number of parallel channels, etc. CDR signaling is well known as shown, for example, in Aung et al. U.S. Patent Publication No. 2001/0033188, published Oct. 25, 2001 and Aung et al. U.S. Patent Publication No. 2003/0212930, published Nov. 13, 2003.
Ordinarily, FEC transmission techniques are able to provide data correction for extended data errors across data links. However, when a reference clock signal is embedded within a serial data stream, extended data errors may also result in a loss of the reference clock signal and a loss of synchronization between the transmitter and the receiver. This loss of synchronization limits the effectiveness of typical FEC techniques.
Programmable logic devices (“PLDs”) are well known as shown, for example, by such references as Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Jefferson et al. U.S. Pat. No. 6,215,326, and Ngai et al. U.S. Pat. No. 6,407,576. In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Rather than having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find PLDs to be an advantageous way to provide various components of what they need to produce.
It would be highly desirable to have the ability to use PLDs to avoid having to always design and build error correcting transmitters and receivers that are specific to each of the many different error correction techniques, protocols, and specifications.